systemverilog.io
Coming soon! The first Python tutorial designed specifically for RTL design, DV, emulation, and validation engineers.
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When learning a new programming language, two things occur.
Your brain constantly tries to draw parallels with another language you are already familiar with. For ASIC/SoC engineers, this is SystemVerilog.
With each new concept you learn, your mind searches for patterns and evaluates how you may apply it to your work.
This tutorial is designed to meet both these needs and address the typical demands and use cases of RTL design, DV, emulation, and validation engineers.
Table of contents
Lists and Dictionaries: Ch 01
Numbers: Ch 02
Strings and Print: Ch 03
Control flow: Ch 04
Files, paths, dirs: Ch 05
Your first Python script: Ch 06
Regular expressions: Ch 07
Functions: Ch 08
Subprocess.run: Ch 09
Passing cmdline arguments : Ch 10
Python tips & tricks: Ch 11
Code editors VSCode, VIM: Appendix A
Installing packages with pip and venv: Appendix B
You'll be notified when each chapter is published